The input/output lines of a dynamic random access memory (RAM) device carry the data from the data in and data out circuits to the bit lines of the memory matrix. During a read operation using balanced sensing, the input/output and input/output lines must be kept at identically the same voltage up until the time they are read. The prior practice for equilibrating the input/output lines involved precharging the lines with a precharge clock signal. The precharge clock signal was bootstrapped above the supply voltage such that the input/output lines were equilibrated to the supply voltage level.
The use of the bootstrapped precharge clock signal to bootstrap the input/output lines above supply voltage has a drawback with some dynamic RAM's, because the bootstrapped clock signal can leak off due to junction leaksge, subthreshold conduction or a number of other problems in the circuit. In addition, after the input/output lines are precharged and the precharge transistors driving the clock signal turn off, the lines are no longer equilibrated if any differential noise comes along on the supply voltage.
A need has thus arisen for an improved circuit to keep the input/output lines at the identical voltage level up until the time these lines are sensed during the read operation.